1. Technical Field
The present invention relates generally to semiconductor devices, and more particularly to a silicon-on-insulator substrate and a method for fabricating a silicon-on-insulator substrate.
2. Description of the Related Art
Silicon-on-insulator (“SOI”) wafers are a basic material for use in the fabrication of advanced complementary metal oxide semiconductor (“CMOS”) circuits. An SOI wafer typically includes a relatively thin monocrystalline layer of silicon exposed at an external major surface of the wafer, a bulk semiconductor region typically consisting essentially of silicon underlying the monocrystalline silicon layer, and a buried oxide (BOX) layer separating the monocrystalline layer from the bulk semiconductor region. The buried oxide layer typically has a thickness of less or about 150 nanometers (nm) and consists essentially of amorphous silicon dioxide.
The separation or isolation of the overlying monocrystalline semiconductor device layer (the “silicon-on-insulator” or “SOI” overlayer) from the underlying bulk semiconductor region of the substrate can result in significant benefits and performance improvements including, for example, less junction capacitance and leakage; greater resistance to ionizing radiation, electrical noise and heat; immunity to CMOS latch-up; and etc. However, forming SOI structures is no simple matter.
Two major processes presently employed for the industrial fabrication of SOI wafers are separation by implanted oxygen (“SIMOX”) and wafer bond and layer transfer. While producing SOI wafers of excellent quality, both of these processes are still relatively costly. In the early 1980's, a process was proposed for making SOI by oxidation of a porous silicon (P—Si) layer below an overlying monocrystalline n-type silicon layer. This method, called fully isolation with porous oxidized silicon (“FIPOS”), required openings to be patterned in the overlying n-type monocrystalline silicon layer to provide access of the electrolyte to the underlying p-type layer. The need for pre-patterning made the FIPOS method unwieldy and expensive. United States Patent Publication No. 2005/0067294A1 to Choe et al. (“Choe et al.”) describes a method of fabricating an SOI wafer via oxidation of a P—Si structure with a depth dependent porosity distribution. In order to create the desired depth distribution of porosity it is first created a depth distribution of p-type doping via implantation of boron ions followed by a thermal annealing for electrical activation of the implanted dopant atoms. Because the doping is made by ion implantation, the boron dopant concentration varies with the depth from the exposed surface according to an nearly Gaussian distribution, increasing from the exposed surface up to a maximum at the projected range of the implantation distribution and then decreasing continuously toward deeper depths. A subsequent anodization process renders the implanted layer porous with a porosity that varies with depth from the exposed surface of the SOI wafer. The layer becomes most porous in portions where the boron dopant concentration peaks. The porosity gradually reduces as the dopant concentration falls lower in regions away from the peak concentration, towards the surface and towards the bulk semiconductor region. A subsequent oxidation process converts the most heavily-doped portions of the substrate into a buried oxide (“BOX”) layer. An implanted portion of the substrate which is not heavily-doped and which lies above the most heavily-doped portion becomes the overlying monocrystalline silicon region above the BOX layer. Another implanted portion which is not heavily-doped and which lies below the most heavily-doped portion becomes a portion of the bulk semiconductor region below the BOX layer.
However the process proposed in Choe et al. can not provide tight control over the BOX layer and SOI thicknesses. This is because the transition from the low porosity to high porosity regions occurs gradually along the depth in consequence of the Gaussian like implant boron doping profile in which the range straggling is tenths of the projected range. Furthermore, the gradual variation in porosity within the buried porous silicon layer makes it difficult to form a BOX layer that has a thickness of less than 100 nanometers (nm).
Forming SOI wafers having a plurality of internal buried oxide layers is also expensive and difficult by bond and etchback or bond and layer transfer methods, because the methods have to be applied at least twice during processing. To do so by an implantation of oxygen method can also be extremely difficult or even impossible because of the difficulty in controlling the depth of implanted ions to within a relatively narrow range of depths for forming each buried oxide layer.